<P> The first 64 I / O registers are accessible through both the I / O and the data address space . They have therefore two different addresses . These are usually written as "0x00 (0x20)" through "0x3F (0x5F)", where the first item is the I / O address and the second, in parentheses, the data address . </P> <P> The special - purpose CPU registers, with the exception of PC, can be accessed as I / O registers . Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 KiB of addressable memory . </P> <Table> <Tr> <Th> Register </Th> <Th> I / O address </Th> <Th> Data address </Th> </Tr> <Tr> <Td> SREG </Td> <Td> 0x3F </Td> <Td> 0x5F </Td> </Tr> <Tr> <Td> SP </Td> <Td> 0x3E: 0x3D </Td> <Td> 0x5E: 0x5D </Td> </Tr> <Tr> <Td> EIND </Td> <Td> 0x3C </Td> <Td> 0x5C </Td> </Tr> <Tr> <Td> RAMPZ </Td> <Td> 0x3B </Td> <Td> 0x5B </Td> </Tr> <Tr> <Td> RAMPY </Td> <Td> 0x3A </Td> <Td> 0x5A </Td> </Tr> <Tr> <Td> RAMPX </Td> <Td> 0x39 </Td> <Td> 0x59 </Td> </Tr> <Tr> <Td> RAMPD </Td> <Td> 0x38 </Td> <Td> 0x58 </Td> </Tr> </Table> <Tr> <Th> Register </Th> <Th> I / O address </Th> <Th> Data address </Th> </Tr>

Program memory constant addressing using the lpm elpm and spm instructions