<P> Intel implemented a similar feature in its Itanium (Merced) processor--having IA - 64 architecture--in 2001, but did not bring it to the more popular x86 processor families (Pentium, Celeron, Xeon, etc .). In the x86 architecture it was first implemented by AMD, as the NX bit, for use by its AMD64 line of processors, such as the Athlon 64 and Opteron . </P> <P> After AMD's decision to include this functionality in its AMD64 instruction set, Intel implemented the similar XD bit feature in x86 processors beginning with the Pentium 4 processors based on later iterations of the Prescott core . The NX bit specifically refers to bit number 63 (i.e. the most significant bit) of a 64 - bit entry in the page table . If this bit is set to 0, then code can be executed from that page; if set to 1, code cannot be executed from that page, and anything residing there is assumed to be data . It is only available with the long mode (64 - bit mode) and legacy Physical Address Extension (PAE) page - table formats, but not x86's original 32 - bit page table format because page table entries in that format lack the 63rd bit used to disable and enable execution . </P> <P> In ARMv6, a new page table entry format was introduced; it includes an "execute never" bit . For ARMv8 - A, VMSAv8 - 64 block and page descriptors, and VMSAv8 - 32 long - descriptor block and page descriptors, for stage 1 translations have "execute never" bits for both privileged and unprivileged modes and block and page descriptors for page 2 translations have a single "execute never" bit; VMSAv8 - 32 short - descriptor translation table descriptors at level 1 have "execute never" bits for both privileged and unprivileged mode and at level 2 have a single "execute never" bit . </P> <P> As of the Fourth Edition of the Alpha Architecture manual, DEC (now HP) Alpha has a Fault on Execute bit in page table entries with the OpenVMS, Tru64 UNIX, and Alpha Linux PALcode . </P>

Nx/xd bit to be enabled for the cpu