<P> The Multibus became a standard of the Institute of Electrical and Electronics Engineers as IEEE standard 796 in 1983 . Sun Microsystems developed the SBus in 1989 to support smaller expansion cards . The easiest way to implement symmetric multiprocessing was to plug in more than one CPU into the shared system bus, which was used through the 1980s . However, the shared bus quickly became the bottleneck and more sophisticated connection techniques were explored . </P> <P> Even in very simple systems, at various times the data bus is driven by the program memory, by RAM, and by I / O devices . To prevent bus contention on the data bus, at any one instant only one device drives the data bus . In very simple systems, only the data bus is required to be a bidirectional bus . In very simple systems, the memory address register always drives the address bus, the control unit always drives the control bus, and an address decoder selects which particular device is allowed to drive the data bus during this bus cycle . In very simple systems, every instruction cycle starts with a READ memory cycle where program memory drives the instruction onto the data bus while the instruction register latches that instruction from the data bus . Some instructions continue with a WRITE memory cycle where the memory data register drives data onto the data bus into the chosen RAM or I / O device . Other instructions continue with another READ memory cycle where the chosen RAM, program memory, or I / O device drives data onto the data bus while the memory data register latches that data from the data bus . </P> <P> More complex systems have a multi-master bus--not only do they have many devices that each drive the data bus, but also have many bus masters that each drive the address bus . The address bus as well as the data bus in bus snooping systems is required to be a bidirectional bus, often implemented as a three - state bus . To prevent bus contention on the address bus, a bus arbiter selects which particular bus master is allowed to drive the address bus during this bus cycle . </P> <P> As CPU design evolved into using faster local buses and slower peripheral buses, Intel adopted the dual independent bus (DIB) terminology, using the external front - side bus to the main system memory, and the internal back - side bus between one or more CPUs and the CPU caches . This was introduced in the Pentium Pro and Pentium II products in the mid to late 1990s . The primary bus for communicating data between the CPU and main memory and input and output devices is called the front - side bus, and the back - side bus accesses the level 2 cache . </P>

Describe bus lines bus width system bus and expansion bus