<P> TTL devices consume substantially more power than equivalent CMOS devices at rest, but power consumption does not increase with clock speed as rapidly as for CMOS devices . Compared to contemporary ECL circuits, TTL uses less power and has easier design rules but is substantially slower . Designers can combine ECL and TTL devices in the same system to achieve best overall performance and economy, but level - shifting devices are required between the two logic families . TTL is less sensitive to damage from electrostatic discharge than early CMOS devices . </P> <P> Due to the output structure of TTL devices, the output impedance is asymmetrical between the high and low state, making them unsuitable for driving transmission lines . This drawback is usually overcome by buffering the outputs with special line - driver devices where signals need to be sent through cables . ECL, by virtue of its symmetric low - impedance output structure, does not have this drawback . </P> <P> The TTL "totem - pole" output structure often has a momentary overlap when both the upper and lower transistors are conducting, resulting in a substantial pulse of current drawn from the power supply . These pulses can couple in unexpected ways between multiple integrated circuit packages, resulting in reduced noise margin and lower performance . TTL systems usually have a decoupling capacitor for every one or two IC packages, so that a current pulse from one TTL chip does not momentarily reduce the supply voltage to another . </P> <P> Several manufacturers now supply CMOS logic equivalents with TTL - compatible input and output levels, usually bearing part numbers similar to the equivalent TTL component and with the same pinouts . For example, the 74HCT00 series provides many drop - in replacements for bipolar 7400 series parts, but uses CMOS technology . </P>

What are the logic low and high levels of ttl ic's