<Table> <Tr> <Td> </Td> <Td> This article needs additional citations for verification . Please help improve this article by adding citations to reliable sources . Unsourced material may be challenged and removed . (May 2016) (Learn how and when to remove this template message) </Td> </Tr> </Table> <Tr> <Td> </Td> <Td> This article needs additional citations for verification . Please help improve this article by adding citations to reliable sources . Unsourced material may be challenged and removed . (May 2016) (Learn how and when to remove this template message) </Td> </Tr> <P> Instruction pipelining is a technique for implementing instruction - level parallelism within a single processor . Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline"), each performed by a different processor units, and occupying different units with parts of different instructions that are then processed in parallel . It allows faster CPU throughput than would otherwise be possible at a given clock rate, but may increase latency due to the added overhead of the pipelining process itself . </P> <P> Central processing units (CPUs) are driven by a clock . Each clock pulse need not do the same thing; rather, logic in the CPU directs successive pulses to different places to perform a useful sequence . There are many reasons that the entire execution of a machine instruction cannot happen at once; in pipelining, effects that cannot happen at the same time are made into dependent steps of the instruction . </P>

In what way do instruction pipeline aid in parallel processing