<P> There are several tools available to computer architects to help explore tradeoffs between the cache cycle time, energy, and area . These tools include the open - source CACTI cache simulator and the open - source SimpleScalar instruction set simulator . Modeling of 2D and 3D SRAM, eDRAM, STT - RAM, ReRAM and PCM caches can be done using the DESTINY tool . </P> <P> A multi-ported cache is a cache which can serve more than one request at a time . When accessing a traditional cache we normally use a single memory address, whereas in a multi-ported cache we may request N addresses at a time--where N is the number of ports that connected through the processor and the cache . The benefit of this is that a pipelined processor may access memory from different phases in its pipeline . Another benefit is that it allows the concept of super-scalar processors through different cache levels . </P>

L1 cache memory is built into a processor