<P> In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction cannot execute in the following clock cycle, and can potentially lead to incorrect computation results . Three common types of hazards are data hazards, structural hazards, and control flow hazards (branching hazards). </P> <P> There are several methods used to deal with hazards, including pipeline stalls / pipeline bubbling, operand forwarding, and in the case of out - of - order execution, the scoreboarding method and the Tomasulo algorithm . </P> <P> Instructions in a pipelined processor are performed in several stages, so that at any given time several instructions are being processed in the various stages of the pipeline, such as fetch and execute . There are many different instruction pipeline microarchitectures, and instructions may be executed out - of - order . A hazard occurs when two or more of these simultaneous (possibly out of order) instructions conflict . </P> <P> Data hazards occur when instructions that exhibit data dependence modify data in different stages of a pipeline . Ignoring potential data hazards can result in race conditions (also termed race hazards). There are three situations in which a data hazard can occur: </P>

Which is the correct condition that determines forwarding is needed