<P> To ensure proper operation of the CPU, the clock period is longer than the maximum time needed for all signals to propagate (move) through the CPU . In setting the clock period to a value well above the worst - case propagation delay, it is possible to design the entire CPU and the way it moves data around the "edges" of the rising and falling clock signal . This has the advantage of simplifying the CPU significantly, both from a design perspective and a component - count perspective . However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster . This limitation has largely been compensated for by various methods of increasing CPU parallelism (see below). </P> <P> However, architectural improvements alone do not solve all of the drawbacks of globally synchronous CPUs . For example, a clock signal is subject to the delays of any other electrical signal . Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit . This has led many modern CPUs to require multiple identical clock signals to be provided to avoid delaying a single signal significantly enough to cause the CPU to malfunction . Another major issue, as clock rates increase dramatically, is the amount of heat that is dissipated by the CPU . The constantly changing clock causes many components to switch regardless of whether they are being used at that time . In general, a component that is switching uses more energy than an element in a static state . Therefore, as clock rate increases, so does energy consumption, causing the CPU to require more heat dissipation in the form of CPU cooling solutions . </P> <P> One method of dealing with the switching of unneeded components is called clock gating, which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very low - power designs . One notable recent CPU design that uses extensive clock gating is the IBM PowerPC - based Xenon used in the Xbox 360; that way, power requirements of the Xbox 360 are greatly reduced . Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether . While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and heat dissipation in comparison with similar synchronous designs . While somewhat uncommon, entire asynchronous CPUs have been built without utilizing a global clock signal . Two notable examples of this are the ARM compliant AMULET and the MIPS R3000 compatible MiniMIPS . </P> <P> Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous ALUs in conjunction with superscalar pipelining to achieve some arithmetic performance gains . While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations . This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for embedded computers . </P>

Explain the structure of cpu with suitable diagram