<P> In the 1970s, analysis of high level languages indicated some complex machine language implementations and it was determined that new instructions could improve performance . Some instructions were added that were never intended to be used in assembly language but fit well with compiled high - level languages . Compilers were updated to take advantage of these instructions . The benefits of semantically rich instructions with compact encodings can be seen in modern processors as well, particularly in the high - performance segment where caches are a central component (as opposed to most embedded systems). This is because these fast, but complex and expensive, memories are inherently limited in size, making compact code beneficial . Of course, the fundamental reason they are needed is that main memories (i.e. dynamic RAM today) remain slow compared to a (high performance) CPU core . </P> <P> While many designs achieved the aim of higher throughput at lower cost and also allowed high - level language constructs to be expressed by fewer instructions, it was observed that this was not always the case . For instance, low - end versions of complex architectures (i.e. using less hardware) could lead to situations where it was possible to improve performance by not using a complex instruction (such as a procedure call or enter instruction), but instead using a sequence of simpler instructions . </P> <P> One reason for this was that architects (microcode writers) sometimes "over-designed" assembly language instructions, i.e. including features which were not possible to implement efficiently on the basic hardware available . This could, for instance, be "side effects" (above conventional flags), such as the setting of a register or memory location that was perhaps seldom used; if this was done via ordinary (non duplicated) internal buses, or even the external bus, it would demand extra cycles every time, and thus be quite inefficient . </P> <P> Even in balanced high - performance designs, highly encoded and (relatively) high - level instructions could be complicated to decode and execute efficiently within a limited transistor budget . Such architectures therefore required a great deal of work on the part of the processor designer in cases where a simpler, but (typically) slower, solution based on decode tables and / or microcode sequencing is not appropriate . At a time when transistors and other components were a limited resource, this also left fewer components and less opportunity for other types of performance optimizations . </P>

In order to implement complex instructions cisc architectures use