<Li> The reset vector for PowerPC / Power Architecture processors is at an effective address of 0x00000100 for 32 - bit processors and 0x0000000000000100 for 64 - bit processors . </Li> <Li> The reset vector for SPARC version 8 processors is at an address of 0x00; the reset vector for SPARC version 9 processors is at an address of 0x20 for power - on reset, 0x40 for watchdog reset, 0x60 for externally initiated reset, and 0x80 for software - initiated reset . </Li> <Li> The reset vector for MIPS32 processors is at virtual address 0xBFC00000, which is located in the last 4 Mbytes of the KSEG1 non-cacheable region of memory . The core enters kernel mode both at reset and when an exception is recognized, hence able to map the virtual address to physical address . </Li>

Contents of cs and ip after applying reset