<Table> Apple A10X Fusion <Tr> <Td_colspan="2"> </Td> </Tr> <Tr> <Th> Produced </Th> <Td> From June 16, 2017 to Present </Td> </Tr> <Tr> <Th> Designed by </Th> <Td> Apple Inc . </Td> </Tr> <Tr> <Th> Common manufacturer (s) </Th> <Td> <Ul> <Li> TSMC </Li> </Ul> </Td> </Tr> <Tr> <Th> Max . CPU clock rate </Th> <Td> to 2.38 GHz </Td> </Tr> <Tr> <Th> Min . feature size </Th> <Td> 10 nm </Td> </Tr> <Tr> <Th> Instruction set </Th> <Td> A64, A32, T32 </Td> </Tr> <Tr> <Th> Microarchitecture </Th> <Td> Hurricane and Zephyr both ARMv8 ‐ A-Compatible </Td> </Tr> <Tr> <Th> Product code </Th> <Td> APL1071 </Td> </Tr> <Tr> <Th> Cores </Th> <Td> Hexa - core (3 × Hurricane + 3 × Zephyr) </Td> </Tr> <Tr> <Th> L1 cache </Th> <Td> Per core: 64 KB instruction + 64 KB data </Td> </Tr> <Tr> <Th> L2 cache </Th> <Td> 8 MB shared </Td> </Tr> <Tr> <Th> Predecessor </Th> <Td> Apple A9X </Td> </Tr> <Tr> <Th> GPU </Th> <Td> 12 core </Td> </Tr> <Tr> <Th> Application </Th> <Td> Mobile </Td> </Tr> <Tr> <Th> Variant </Th> <Td> Apple A10 Fusion </Td> </Tr> </Table> <Tr> <Th> Produced </Th> <Td> From June 16, 2017 to Present </Td> </Tr> <Tr> <Th> Designed by </Th> <Td> Apple Inc . </Td> </Tr> <Tr> <Th> Common manufacturer (s) </Th> <Td> <Ul> <Li> TSMC </Li> </Ul> </Td> </Tr>

A10x fusion chip with 64‐bit architecture embedded m10 coprocessor