<P> As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on - chip cache . Price - sensitive designs used this to pull the entire cache hierarchy on - chip, but by the 2010s some of the highest - performance designs returned to having large off - chip caches, which is often implemented in eDRAM and mounted on a multi-chip module, as a fourth cache level . </P> <P> The benefits of L3 and L4 caches depend on the application's access patterns . Examples of products incorporating L3 and L4 caches include the following: </P> <Ul> <Li> Alpha 21164 (1995) has 1 to 64 MB off - chip L3 cache . </Li> <Li> IBM POWER4 (2001) has off - chip L3 caches of 32 MB per processor, shared among several processors . </Li> <Li> Itanium 2 (2003) has a 6 MB unified level 3 (L3) cache on - die; the Itanium 2 (2003) MX 2 module incorporates two Itanium 2 processors along with a shared 64 MB L4 cache on a multi-chip module that was pin compatible with a Madison processor . </Li> <Li> Intel's Xeon MP product codenamed "Tulsa" (2006) features 16 MB of on - die L3 cache shared between two processor cores . </Li> <Li> AMD Phenom II (2008) has up to 6 MB on - die unified L3 cache . </Li> <Li> Intel Core i7 (2008) has an 8 MB on - die unified L3 cache that is inclusive, shared by all cores . </Li> <Li> Intel Haswell CPUs with integrated Intel Iris Pro Graphics have 128 MB of eDRAM acting essentially as an L4 cache . </Li> </Ul> <Li> Alpha 21164 (1995) has 1 to 64 MB off - chip L3 cache . </Li>

How many levels of cache memory in the intel i7 processor