<P> CMOS circuits use a combination of p - type and n - type metal--oxide--semiconductor field - effect transistor (MOSFETs) to implement logic gates and other digital circuits . Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of silicon of between 10 and 400 mm . </P> <P> CMOS always uses all enhancement - mode MOSFETs (in other words, a zero gate - to - source voltage turns the transistor off). </P> <P> CMOS circuits are constructed in such a way that all P - type metal - oxide - semiconductor (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor . Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor . The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied . On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied . CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together . A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse . This arrangement greatly reduces power consumption and heat generation . However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another . This induces a brief spike in power consumption and becomes a serious issue at high frequencies . </P> <P> The image on the right shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state . This limits the current that can flow from Q to ground . The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output . Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small . The output, therefore, registers a high voltage . </P>

When does a cmos gate take more current
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