<P> A device that is distantly related to the DAC is the digitally controlled potentiometer, used to control an analog signal digitally . </P> <P> A one - bit mechanical actuator assumes two positions: one when on, another when off . The motion of several one - bit actuators can be combined and weighted with a whiffletree mechanism to produce finer steps . The IBM Selectric typewriter uses such as system . When a typewriter key is pressed, it moves a metal bar (interposer) down that has several lugs . The lugs are the information bits . When a key is pressed, its interposer is moved by the motor . If a lug is present at one position, it will move the corresponding selector bail (bar); if the lug is not present, the selector bail stays where it is . The discrete motions of the bails are combined by a whiffle tree, and the output controls the rotation and tilt of the Selectric's typeball . </P> <P> The most common types of electronic DACs are: </P> <Ul> <Li> The pulse - width modulator, the simplest DAC type . A stable current or voltage is switched into a low - pass analog filter with a duration determined by the digital input code . This technique is often used for electric motor speed control, but has many other applications as well . </Li> <Li> Oversampling DACs or interpolating DACs such as the delta - sigma DAC, use a pulse density conversion technique . The oversampling technique allows for the use of a lower resolution DAC internally . A simple 1 - bit DAC is often chosen because the oversampled result is inherently linear . The DAC is driven with a pulse - density modulated signal, created with the use of a low - pass filter, step nonlinearity (the actual 1 - bit DAC), and negative feedback loop, in a technique called delta - sigma modulation . This results in an effective high - pass filter acting on the quantization (signal processing) noise, thus steering this noise out of the low frequencies of interest into the megahertz frequencies of little interest, which is called noise shaping . The quantization noise at these high frequencies is removed or greatly attenuated by use of an analog low - pass filter at the output (sometimes a simple RC low - pass circuit is sufficient). Most very high resolution DACs (greater than 16 bits) are of this type due to its high linearity and low cost . Higher oversampling rates can relax the specifications of the output low - pass filter and enable further suppression of quantization noise . Speeds of greater than 100 thousand samples per second (for example, 192 kHz) and resolutions of 24 bits are attainable with delta - sigma DACs . A short comparison with pulse - width modulation shows that a 1 - bit DAC with a simple first - order integrator would have to run at 3 THz (which is physically unrealizable) to achieve 24 meaningful bits of resolution, requiring a higher - order low - pass filter in the noise - shaping loop . A single integrator is a low - pass filter with a frequency response inversely proportional to frequency and using one such integrator in the noise - shaping loop is a first order delta - sigma modulator . Multiple higher order topologies (such as MASH) are used to achieve higher degrees of noise - shaping with a stable topology . </Li> <Li> The binary - weighted DAC, which contains individual electrical components for each bit of the DAC connected to a summing point . These precise voltages or currents sum to the correct output value . This is one of the fastest conversion methods but suffers from poor accuracy because of the high precision required for each individual voltage or current . Such high - precision components are expensive, so this type of converter is usually limited to 8 - bit resolution or less . <Ul> <Li> Switched resistor DAC contains a parallel resistor network . Individual resistors are enabled or bypassed in the network based on the digital input . </Li> <Li> Switched current source DAC, from which different current sources are selected based on the digital input . </Li> <Li> Switched capacitor DAC contains a parallel capacitor network . Individual capacitors are connected or disconnected with switches based on the input . </Li> </Ul> </Li> <Li> The R - 2R ladder DAC which is a binary - weighted DAC that uses a repeating cascaded structure of resistor values R and 2R . This improves the precision due to the relative ease of producing equal valued - matched resistors (or current sources). </Li> <Li> The Successive - Approximation or Cyclic DAC, which successively constructs the output during each cycle . Individual bits of the digital input are processed each cycle until the entire input is accounted for . </Li> <Li> The thermometer - coded DAC, which contains an equal resistor or current - source segment for each possible value of DAC output . An 8 - bit thermometer DAC would have 255 segments, and a 16 - bit thermometer DAC would have 65,535 segments . This is perhaps the fastest and highest precision DAC architecture but at the expense of high cost . Conversion speeds of> 1 billion samples per second have been reached with this type of DAC . </Li> <Li> Hybrid DACs, which use a combination of the above techniques in a single converter . Most DAC integrated circuits are of this type due to the difficulty of getting low cost, high speed and high precision in one device . <Ul> <Li> The segmented DAC, which combines the thermometer - coded principle for the most significant bits and the binary - weighted principle for the least significant bits . In this way, a compromise is obtained between precision (by the use of the thermometer - coded principle) and number of resistors or current sources (by the use of the binary - weighted principle). The full binary - weighted design means 0% segmentation, the full thermometer - coded design means 100% segmentation . </Li> </Ul> </Li> <Li> Most DACs, shown earlier in this list, rely on a constant reference voltage to create their output value . Alternatively, a multiplying DAC takes a variable input voltage for their conversion . This puts additional design constraints on the bandwidth of the conversion circuit . </Li> </Ul>

Explain briefly the digital to analog conversion process for binary weighted resistor