<P> In electronics, a sample and hold (S / H, also "follow - and - hold") circuit is an analog device that samples (captures, grabs) the voltage of a continuously varying analog signal and holds (locks, freezes) its value at a constant level for a specified minimum period of time . Sample and hold circuits and related peak detectors are the elementary analog memory devices . They are typically used in analog - to - digital converters to eliminate variations in input signal that can corrupt the conversion process . </P> <P> A typical sample and hold circuit stores electric charge in a capacitor and contains at least one switching device such as a FET (field effect transistor) switch and normally one operational amplifier . To sample the input signal the switch connects the capacitor to the output of a buffer amplifier . The buffer amplifier charges or discharges the capacitor so that the voltage across the capacitor is practically equal, or proportional to, input voltage . In hold mode the switch disconnects the capacitor from the buffer . The capacitor is invariably discharged by its own leakage currents and useful load currents, which makes the circuit inherently volatile, but the loss of voltage (voltage drop) within a specified hold time remains within an acceptable error margin . </P>

Sample and hold circuit in adc s are designed to
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