<P> Since 2005 / 2006, considering an architecture in which 4 processors share a chipset, the DIB is composed by two busses, each of them is shared among two CPUs . The theoretical bandwidth is doubled compared to a shared front - side bus up to 12.8 GB / s in the best case . However, the snoop information useful to guarantee the cache coherence of shared data located in different caches have to be sent in broadcast, reducing the available bandwidth . To mitigate this limitation, a snoop filter was inserted in the chipset, in order to cache the snoop information . </P> <P> Modern personal and server computers use higher - performance interconnection technologies such as HyperTransport and Intel QuickPath Interconnect, while the system bus architecture continued to be used on simpler embedded microprocessors . The systems bus can even be internal to a single integrated circuit, producing a system - on - a-chip . Examples include AMBA, CoreConnect, and Wishbone . </P>

With a well labelled diagram describe the cpu memory read operation