<P> Some designs use a combination of hardwired design and microcode for the control unit . </P> <P> Some CPU designs use a writable control store--they compile the instruction set to a writable RAM or flash inside the CPU (such as the Rekursiv processor and the Imsys Cjip), or an FPGA (reconfigurable computing). </P> <P> An ISA can also be emulated in software by an interpreter . Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless the hardware running the emulator is an order of magnitude faster . Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready . </P> <P> Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set . For example, many implementations of the instruction pipeline only allow a single memory load or memory store per instruction, leading to a load - store architecture (RISC). For another example, some early ways of implementing the instruction pipeline led to a delay slot . </P>

A list of instruction used by computer is called