<Tr> <Td> 0 </Td> <Td> </Td> </Tr> <Tr> <Td> </Td> <Td> </Td> </Tr> <P> These tables show that when S = 0 (\ displaystyle \ scriptstyle S = 0) then Z = A (\ displaystyle \ scriptstyle Z = A) but when S = 1 (\ displaystyle \ scriptstyle S = 1) then Z = B (\ displaystyle \ scriptstyle Z = B). A straightforward realization of this 2 - to - 1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate . While this is mathematically correct, it should be noted that a direct physical implementation would be prone to race conditions that require additional gates to suppress . </P> <P> Larger multiplexers are also common and, as stated above, require ⌈ log 2 ⁡ (n) ⌉ (\ displaystyle \ scriptstyle \ left \ lceil \ log _ (2) (n) \ right \ rceil) selector pins for n (\ displaystyle n) inputs . Other common sizes are 4 - to - 1, 8 - to - 1, and 16 - to - 1 . Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control a number of inputs for the given number of selector inputs . </P>

Where does the output unit send the data