<P> The 8086 was sequenced using a mixture of random logic and microcode and was implemented using depletion - load nMOS circuitry with approximately 20,000 active transistors (29,000 counting all ROM and PLA sites). It was soon moved to a new refined nMOS manufacturing process called HMOS (for High performance MOS) that Intel originally developed for manufacturing of fast static RAM products . This was followed by HMOS - II, HMOS - III versions, and, eventually, a fully static CMOS version for battery powered devices, manufactured using Intel's CHMOS processes . The original chip measured 33 mm2 and minimum feature size was 3.2 μm . </P> <P> The architecture was defined by Stephen P. Morse with some help and assistance by Bruce Ravenel (the architect of the 8087) in refining the final revisions . Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware - level development team and Bill Pohlman the manager for the project . The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the Intel 286 and the Intel 386, all of which eventually became known as the x86 family . (Another reference is that the PCI Vendor ID for Intel devices is 8086 .) </P> <Table> <Tr> <Td> Intel 8086 registers </Td> </Tr> <Tr> <Td> <Table> <Tr> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> (bit position) </Td> </Tr> <Tr> <Td_colspan="21"> Main registers </Td> </Tr> <Tr> <Td_colspan="4"> </Td> <Td_colspan="8"> AH </Td> <Td_colspan="8"> AL </Td> <Td> AX (primary accumulator) </Td> </Tr> <Tr> <Td_colspan="4"> </Td> <Td_colspan="8"> BH </Td> <Td_colspan="8"> BL </Td> <Td> BX (base, accumulator) </Td> </Tr> <Tr> <Td_colspan="4"> </Td> <Td_colspan="8"> CH </Td> <Td_colspan="8"> CL </Td> <Td> CX (counter, accumulator) </Td> </Tr> <Tr> <Td_colspan="4"> </Td> <Td_colspan="8"> DH </Td> <Td_colspan="8"> DL </Td> <Td> DX (accumulator, other functions) </Td> </Tr> <Tr> <Td_colspan="21"> Index registers </Td> </Tr> <Tr> <Td_colspan="4"> 0 0 0 0 </Td> <Td_colspan="16"> SI </Td> <Td> Source Index </Td> </Tr> <Tr> <Td_colspan="4"> 0 0 0 0 </Td> <Td_colspan="16"> DI </Td> <Td> Destination Index </Td> </Tr> <Tr> <Td_colspan="4"> 0 0 0 0 </Td> <Td_colspan="16"> BP </Td> <Td> Base Pointer </Td> </Tr> <Tr> <Td_colspan="4"> 0 0 0 0 </Td> <Td_colspan="16"> SP </Td> <Td> Stack Pointer </Td> </Tr> <Tr> <Td_colspan="21"> Program counter </Td> </Tr> <Tr> <Td_colspan="4"> 0 0 0 0 </Td> <Td_colspan="16"> IP </Td> <Td> Instruction Pointer </Td> </Tr> <Tr> <Td_colspan="21"> Segment registers </Td> </Tr> <Tr> <Td_colspan="16"> CS </Td> <Td_colspan="4"> 0 0 0 0 </Td> <Td> Code Segment </Td> </Tr> <Tr> <Td_colspan="16"> DS </Td> <Td_colspan="4"> 0 0 0 0 </Td> <Td> Data Segment </Td> </Tr> <Tr> <Td_colspan="16"> ES </Td> <Td_colspan="4"> 0 0 0 0 </Td> <Td> Extra Segment </Td> </Tr> <Tr> <Td_colspan="16"> SS </Td> <Td_colspan="4"> 0 0 0 0 </Td> <Td> Stack Segment </Td> </Tr> <Tr> <Td_colspan="21"> Status register </Td> </Tr> <Tr> <Td_colspan="4"> </Td> <Td> - </Td> <Td> - </Td> <Td> - </Td> <Td> - </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> </Td> <Td> Z </Td> <Td> - </Td> <Td> </Td> <Td> - </Td> <Td> </Td> <Td> - </Td> <Td> </Td> <Td> Flags </Td> </Tr> </Table> </Td> </Tr> </Table> <Tr> <Td> Intel 8086 registers </Td> </Tr>

List out the basic addressing modes of the intel 8086 microprocessor