<P> It is most common to regard subsequent inputs as being applied through a cascade of binary exclusive - or operations: the first two signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together with the third signal, and so on for any remaining signals . The result is a circuit that outputs a 1 when the number of 1s at its inputs is odd, and a 0 when the number of incoming 1s is even . This makes it practically useful as a parity generator or a modulo - 2 adder . </P> <P> For example, the 74LVC1G386 microchip is advertised as a three - input logic gate, and implements a parity generator . </P> <P> The XOR logic gate can be used as a one - bit adder that adds any two bits together to output one bit . For example, if we add 1 plus 1 in binary, we expect a two - bit answer, 10 (i.e. 2 in decimal). Since the trailing sum bit in this output is achieved with XOR, the preceding carry bit is calculated with an AND gate . This is the main principle in Half Adders . A slightly larger Full Adder circuit may be chained together in order to add longer binary numbers . </P> <P> Pseudo-random number (PRN) generators, specifically Linear feedback shift registers, are defined in terms of the exclusive - or operation . Hence, a suitable setup of XOR gates can model a linear feedback shift register, in order to generate random numbers . </P>

The combination of gates shown in the fig. below produces