<Dl> <Dt> Page size versus page table size </Dt> <Dd> A system with a smaller page size uses more pages, requiring a page table that occupies more space . For example, if a 2 virtual address space is mapped to 4 KiB (2 bytes) pages, the number of virtual pages is 2 = (2 / 2). However, if the page size is increased to 32 KiB (2 bytes), only 2 pages are required . A multi-level paging algorithm can decrease the memory cost of allocating a large page table for each process by further dividing the page table up into smaller tables, effectively paging the page table . </Dd> </Dl> <Dt> Page size versus page table size </Dt> <Dd> A system with a smaller page size uses more pages, requiring a page table that occupies more space . For example, if a 2 virtual address space is mapped to 4 KiB (2 bytes) pages, the number of virtual pages is 2 = (2 / 2). However, if the page size is increased to 32 KiB (2 bytes), only 2 pages are required . A multi-level paging algorithm can decrease the memory cost of allocating a large page table for each process by further dividing the page table up into smaller tables, effectively paging the page table . </Dd> <Dl> <Dt> Page size versus TLB usage </Dt> <Dd> Since every access to memory must be mapped from virtual to physical address, reading the page table every time can be quite costly . Therefore, a very fast kind of cache, the Translation Lookaside Buffer (TLB), is often used . The TLB is of limited size, and when it cannot satisfy a given request (a TLB miss) the page tables must be searched manually (either in hardware or software, depending on the architecture) for the correct mapping . Larger page sizes mean that a TLB cache of the same size can keep track of larger amounts of memory, which avoids the costly TLB misses . </Dd> </Dl>

Why page size is power of 2 in os
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