<P> Thus, while a von Neumann architecture is visible in some contexts, such as when data and code come through the same memory controller, the hardware implementation gains the efficiencies of the Harvard architecture for cache accesses and at least some main memory accesses . </P> <P> In addition, CPUs often have write buffers which let CPUs proceed after writes to non-cached regions . The von Neumann nature of memory is then visible when instructions are written as data by the CPU and software must ensure that the caches (data and instruction) and write buffer are synchronized before trying to execute those just - written instructions . </P> <P> The principal advantage of the pure Harvard architecture--simultaneous access to more than one memory system--has been reduced by modified Harvard processors using modern CPU cache systems . Relatively pure Harvard architecture machines are used mostly in applications where trade - offs, like the cost and power savings from omitting caches, outweigh the programming penalties from featuring distinct code and data address spaces . </P> <Ul> <Li> Digital signal processors (DSPs) generally execute small, highly optimized audio or video processing algorithms . They avoid caches because their behavior must be extremely reproducible . The difficulties of coping with multiple address spaces are of secondary concern to speed of execution . Consequently, some DSPs feature multiple data memories in distinct address spaces to facilitate SIMD and VLIW processing . Texas Instruments TMS320 C55x processors, for one example, feature multiple parallel data buses (two write, three read) and one instruction bus . </Li> <Li> Microcontrollers are characterized by having small amounts of program (flash memory) and data (SRAM) memory, and take advantage of the Harvard architecture to speed processing by concurrent instruction and data access . The separate storage means the program and data memories may feature different bit widths, for example using 16 - bit wide instructions and 8 - bit wide data . They also mean that instruction prefetch can be performed in parallel with other activities . Examples include the PIC by Microchip Technology, Inc. and the AVR by Atmel Corp (now part of Microchip Technology). </Li> </Ul>

The harvard architecture for micro-controllers added which additional bus