<P> DMA in Cell is fully cache coherent (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the standard sense). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks . The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size . According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second . </P> <P> Processors with scratchpad memory and DMA (such as digital signal processors and the Cell processor) may benefit from software overlapping DMA memory operations with processing, via double buffering or multibuffering . For example, the on - chip memory is split into two buffers; the processor may be operating on data in one, while the DMA engine is loading and storing data in the other . This allows the system to avoid memory latency and exploit burst transfers, at the expense of needing a predictable memory access pattern . </P>

Dma allows the transfer of data directly between external devices