<Li> The execution of all four instructions is completed </Li> <P> A pipelined processor may deal with hazards by stalling and creating a bubble in the pipeline, resulting in one or more cycles in which nothing useful happens . </P> <P> In the illustration at right, in cycle 3, the processor cannot decode the purple instruction, perhaps because the processor determines that decoding depends on results produced by the execution of the green instruction . The green instruction can proceed to the Execute stage and then to the Write - back stage as scheduled, but the purple instruction is stalled for one cycle at the Fetch stage . The blue instruction, which was due to be fetched during cycle 3, is stalled for one cycle, as is the red instruction after it . </P> <P> Because of the bubble (the blue ovals in the illustration), the processor's Decode circuitry is idle during cycle 3 . Its Execute circuitry is idle during cycle 4 and its Write - back circuitry is idle during cycle 5 . </P>

The pc is incremented by 4 during the write-back (wb) stage of an instruction execution